1. Technical Field
The present invention relates generally to memory circuits and more specifically to a semiconductor memory having write-cycles
2. Background Art
Microprocessors are used in many applications including personal computers and other electronic systems. A goal of any microprocessor is to process information quickly. One problem has been the communication rate between a microprocessor and main memory. The instructions to be executed by the microprocessor and the data on which operations implemented by the instructions are to be performed are stored at addresses within main memory. To access instructions and data, the microprocessor transmits addresses to main memory. The main memory decodes the address and makes the contents at the requested address available for reading and/or writing. The time required for the microprocessor to transmit an address to main memory and receive the respective contents therefrom can significantly constrain system performance.
One technique, which is used to increase the speed with which the microprocessor processes information, is to provide the microprocessor with an architecture, which includes a fast local memory called a cache memory
A cache memory is a small, fast memory that keeps copies of recently used data or instructions. When these items are reused, they can be accessed from the cache memory instead of main memory. Instead of operating at slower main memory access speeds, the microprocessor can operate at faster cache memory access speeds most of the time.
In order to further increase performance, microprocessors have come to include more than one cache memory on the same semiconductor substrate as the microprocessor.
The most commonly used cache memories use static random access memory (SRAM) circuitry, which provide high densities using wordlines and bitlines to access SRAM memory cells. However, SRAM circuitry requires minimal read/write circuit architectures. To support minimal architectures, a memory cell is accessed by pre-charging a row wordline wire and enabling a selected column-gating transistor to read the value from the memory cell.
The use of memory circuits in battery-operated and other low-voltage devices make it desirable to operate the memory circuits at lowest voltage possible. Typically, when read or write operations are done in memory arrays, the wordline is set high with the power applied while the information stored in the memory cells is read by being transferred onto bitlines or information on the bitlines is written by being stored in the memory cells. For read operations, bitlines are then read by a sense-amp. For write operations, information on the bitlines change the held charge in the memory cell.
In a read-modify-write scheme, reading and writing occur in the same clock cycle, reading in the first half, writing in the second. A major problem occurs when the bitline is pulled low in the course of the write instruction. The same bitline must be fully pre-charged before the beginning of the next full cycle in anticipation of a read phase. Beginning the pre-charge process too late can corrupt the next read operation, whereas beginning the pre-charge process too early before the write operation has finished can end up storing an improper value.
Further complicating the process is the small amount of time the operations must occur in. Although pre-charging is a relatively quick process, at a clock speed 2 GHz, the entire write phase including writing and pre-charging, must take place in less 250 picoseconds. As clock speeds increase in the future, it becomes increasingly important to know exactly when the write operation has completed and it is safe to begin pre-charging. Unfortunately, there is no way to directly monitor an individual memory cell within a densely packed memory array without adding more wires and adversely affecting the density and speed of the memory. Thus, as speed increases, the reliability decreases because of the uncertainty of when pre-charging should begin.
A solution to this problem has been long sought but has long eluded those skilled in the art.
The present invention provides a memory system having a memory cell subject to read and write operations with shadow circuitry including a shadow cell configured to parallel operation of the memory cell. A wordline is connected to the memory cell and bitlines are connected to the memory cell and the shadow cell. Sense circuitry is connected to the bitlines for receiving data from the memory cell. An interlock cell is connected to the sense circuitry and the shadow cell to determine an occurrence of a non-redundant write operation, to provide the non-redundant write operation to the shadow cell, and to have the shadow cell prepare the bitlines for a read operation upon completion of the non-redundant write operation. This makes it possible to know when a write operation has been completed and a safe pre-charging of the bitlines can be performed.
Certain embodiments of the invention have other advantages in addition to or in place of those mentioned above. The advantages will become apparent to those skilled in the art from a reading of the following detailed description when taken with reference to the accompanying drawings.